As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in various electronic devices. Generally, a solid state storage device comprises a controlling circuit and a non-volatile memory. Moreover, the solid state storage device is also referred as a flash memory.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 comprises a control circuit 101 and a memory cell array 105.
The solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is a USB bus, an SATA bus, a PCIe bus, or the like. Moreover, the control circuit 101 is connected with the memory cell array 105 through an internal bus 113. According to a write command from the host 14, the control circuit 101 stores a write data from the host 14 to the memory cell array 105. According to a read command from the host 14, the control circuit 101 acquires a read data from the memory cell array 105. In addition, the read data is transmitted to the host 14 through the external bus 12.
The memory cell array 105 comprises plural memory cells. Each memory cell comprises a floating gate transistor. Depending on the data amount to be stored per memory cell, the memory cells may be classified into three types, i.e. a single-level cell (SLC), a multi-level cell (MLC) and a triple-level cell (TLC). The SLC can store only one bit of data per cell. The MLC can store two bits of data per cell. The TLC can store three bits of data per cell.
In case that the memory cell array has the same number of memory cells, the storage amount of the TLC memory cell array is eight times the storage amount of the SLC memory cell array.
FIG. 2 schematically illustrates a data layout of the memory cell array of the conventional solid state storage device. Generally, the memory cell array 105 is divided into plural blocks. Each block is divided into plural pages.
For example, as shown in FIG. 2, the memory cell array is an 8-channel, 1-chip enable memory cell array, which is also referred as the 8CH1CE memory cell array. The memory cell array is divided into N logical blocks. Each logical block is divided into 8 pages, which are indicated as P0˜P7. For example, N is 1400. The storage capacity of each page is 256 Mbyte. Consequently, the storage capacity of the memory cell array is about 256 Gbyte. In addition, this memory cell array is a TLC memory cell array.
For assuring the data accuracy of the memory array, the last page in each logical block of the memory cell array 105 (i.e., P7) is used as a parity page for storing parity data.
While the control circuit 101 stores the write data into the memory cell array 105, the write data is stored into the first seven pages P0˜P6 of each logical block only. Moreover, the control circuit 101 performs a specified operation on the data of the first seven pages. The result of the operation is used as parity data to be stored in the last page P7 (i.e., the parity page).
For example, after the control circuit 101 performs an XOR operation on the first bits of the data of the first seven pages P0˜P6, the output value of the XOR operation is used as the first bit of the parity data. Similarly, after the control circuit 101 performs an XOR operation on the second bits of the data of the first seven pages P0˜P6, the output value of the XOR operation is used as the second bit of the parity data. The rest may be deduced by analogy. Consequently, the parity data to be stored in the last page P7 (i.e., the parity page) is acquired by control circuit 101.
Moreover, the parity data in the parity page can be used to verify whether the data of the first seven pages in the logical block are erroneous or not. For example, a verify-after-write action will be described as follows.
After the control circuit 101 writes the data into the logical block, the verify-after-write action is performed. Meanwhile, the control circuit 101 reads all data in the logic block (i.e., the data of the pages P0˜P7) in order to assure the accuracy of the write data.
If the output value of the XOR operation on the first bits of the data of the first seven pages P0˜P6 is identical to the first bit of the parity data in the last page P7, the control circuit 101 confirms that all of the first bits of the data of the first seven pages are accurate. Similarly, if the output value of the XOR operation on the second bits of the data of the first seven pages P0˜P6 is identical to the second bit of the parity data in the last page P7, the control circuit 101 confirms that all of the second bits of the data of the first seven pages are accurate. The rest may be deduced by analogy.
If the results of the XOR operation on the data of the first seven pages are all identical to the parity data in the last page, the control circuit 101 confirms that the data of the first seven pages are accurate. It means that the verify-after-write action passes. Whereas, if the results of the XOR operation on the data of the first seven pages are not identical to the parity data in the last page, the control circuit 101 judges that the data of the first seven pages are erroneous. It means that the verify-after-write action fails.
Besides, when the host 14 issues a read command to the control circuit 101 to read the data in a specified page of a logical block, the control circuit 101 has to read to all data from the logical block and verify whether the data of the specified page are accurate. After the control circuit 101 confirms that the data of the specified page are accurate, the control circuit 101 issues the data of the specified page to the host 14.
If the control circuit 101 judges that the data of the specified page are erroneous, the control circuit 101 performs the XOR operation to correct the data of the specified page. That is, the control circuit 101 performs the XOR operation to restore the data of the specified page according to the data of the other seven pages, including the parity data in the last page, in the logical block.
As mentioned above, the last page of each logical block in the memory cell array 105 of the solid state storage device 10 is used as the parity page for storing parity data. In the memory cell array of FIG. 2, the parity strip ratio is 1:7.
As known, the parity page occupies the storage space of the write data from the host. For saving the storage space of the parity page, the data layout of the memory cell array should be modified. FIG. 3 schematically illustrates another data layout of the memory cell array of the conventional solid state storage device. For example, as shown in FIG. 3, the memory cell array is an 8-channel, 2-chip enable memory cell array, which is also referred as the 8CH2CE memory cell array. The storage amount of the memory cell array as shown in FIG. 3 is two times the storage amount of the memory cell array as shown in FIG. 2.
The memory cell array is divided into N logical blocks. Each logical block is divided into 16 pages, which are indicated as P0˜P15. For example, N is 1400. The storage capacity of each page is 256 Mbyte. Consequently, the storage capacity of the memory cell array is about 512 Gbyte. In addition, this memory cell array is a TLC memory cell array.
Similarly, for assuring the data accuracy of the memory array, the last page in each logical block of the memory cell array 105 (i.e., P15) is used as a parity page for storing parity data. In the memory cell array of FIG. 3, the parity strip ratio is 1:15.
In the memory cell array of FIG. 3, the storage space of the parity page is saved. However, the control circuit 101 has to read to all pages P0˜P15 from the logical block to verify whether the data of the specified page are accurate through the XOR operation, or to perform the XOR operation to restore the data of the specified page. Since the amount of data to be read by the control circuit increases, the time period for performing the verifying process or the time period of restoring the data is extended.
An 8-channel, 4-chip enable memory cell array, which is also referred as the 8CH4CE memory cell array, is another type of memory cell array. Each logical block is divided into 32 pages, which are indicated as P0˜P31. The storage capacity of the memory cell array is about 1024 Gbyte. The parity strip ratio of this memory cell array is 1:31.
As mentioned above, the storage space of the conventional memory cell array is influenced by the parity page. In the memory cell array of FIG. 2, one-eighth of the storage space is not used for storing the write data from the host. In the memory cell array of FIG. 3, one-sixteenth of the storage space is not used for storing the write data from the host.